Field of the Invention
The invention lies in the field of integrated circuits. The invention relates to a semiconductor memory having at least one memory bank including dynamic memory cells. The memory cells are disposed in rows and are addressable through a word line. When a memory cell is accessed, the respective word line is activated. A control device provides for a refresh operation. The invention additionally relates to a method for operating such a semiconductor memory.
Dynamic semiconductor memories contain memory cells that conventionally include a selection transistor and also a storage capacitor. The memory cells are disposed in a plurality of memory banks. A memory bank contains all the functional units for performing an access to a memory cell. The memory banks can be operated independently of one another. Within a memory bank, the memory cells are disposed in rows. All the memory cells of a row are addressable by a word line. When the word line is activated, the selection transistors of the memory cell are turned on so that the storage capacitor is respectively connected to a bit line. The stored data value is available on the bit line ready for read-out after amplification by a sense amplifier.
Unavoidable leakage currents in the semiconductor chip reduce the quantity of charge that is stored in the storage capacitor and represents either a logic xe2x80x9c1xe2x80x9d or a logic xe2x80x9c0xe2x80x9d. The charge content of the memory cell must, therefore, be refreshed from time to time. The refresh interval is typically 64 milliseconds. During the refresh operation, for all the word lines and the memory cells of a memory bank that are connected thereto, in each case after the activation of the word line, the data content of the memory cells is amplified in the sense amplifier. Afterward, the amplified level is written back to the memory cell. Finally, the word line is deactivated, so that the selection transistors of the memory cells connected thereto are turned off.
In system applications with dynamic semiconductor memories, for example, in the case of personal computers, a memory controller is provided as a separate semiconductor chip to control the accesses to the dynamic semiconductor memory. Conventional memory controllers store the address of the respectively open row for one of the open memory banks of an addressed semiconductor memory. Because, during the processing of programs or data stored in the semiconductor memory, it can be assumed with high probability that subsequent memory accesses are made to successive memory addresses and, hence, adjacent memory cells, it is possible, due to the buffer-storage of the address of the already activated row of a memory bank, in principle, to accelerate the access to the memory bank.
In today""s system applications, however, endeavors are made to the effect that, in the event of a read access to the semiconductor memory, usually relatively large data blocks are read out and buffer-stored in a fast buffer memory, a so-called cache memory. By way of example, a sufficiently short loop of an operating program is loaded completely from the dynamic semiconductor memory into the cache memory, which is significantly faster by comparison, and is multiply iterated. Even if the subsequent access to the dynamic semiconductor memory is effected compared with a preceding access to adjacent memory cells that are spatially close together, so much time has already elapsed through the processing of the program loop of the main memory that a refresh operation has been necessary in the meantime. Because all the word lines are run through during the refresh operation, without further measures, the information about the activated word line that was previously ready for access is no longer present on the semiconductor memory. If the memory controller has stored the address of the previously activated word line, the address must be retransmitted to the semiconductor memory to reactivate there the row that was activated before the refresh operation. Such is true because, in accordance with the specification for synchronously operating dynamic semiconductor memories, so-called SDRAMs, before a refresh command can be applied to the SDRAM, all the memory banks must be put into the precharged state, the so-called precharge all state, so that all the word lines are deactivated and set to reference-ground potential. Only if the memory controller has corresponding registers in which the address of the activated row has been buffer-stored and transmits the address with a corresponding activate command after a refresh operation for the relevant memory bank to the dynamic semiconductor memory is such a memory bank, and, therein, the relevant row or word line, then activated. On one hand, the process has the disadvantage that the access speed is reduced because, on the semiconductor memory itself, the information about the open row is lost due to the refresh operation and the information has to be retransmitted from the memory controller after the refresh operation. On the other hand, additional data traffic is generated that burdens the memory bus in the system and, therefore, also impairs the operating speed.
It is accordingly an object of the invention to provide a dynamic semiconductor memory with refresh that overcomes the hereinafore-mentioned disadvantages of the heretofore-known devices and methods of this general type and that improves a dynamic semiconductor memory of the type mentioned in the introduction to the effect memory accesses faster, in particular, the intention is that a refresh operation will not impair the access readiness of the dynamic semiconductor memory more than necessary.
With the foregoing and other objects in view, there is provided, in accordance with the invention, a semiconductor memory including at least one memory bank having dynamic memory cells disposed in rows and word lines, the memory cells of one of the rows being connected to and addressed by one of the word lines, the one word line being activated for access of one of the memory cells connected to the one word line, a memory element connected to the memory bank and storing an address associated with an activated one of the word lines, and a control device connected to the memory bank, the control device programmed to refresh the memory bank by resetting all of the word lines of the memory bank and to activate one of the word lines having the address stored in the memory element after refreshing the memory bank.
With the objects of the invention in view, there is also provided a method for operating a semiconductor memory including the steps of providing at least one memory bank having dynamic memory cells disposed in rows, addressing the memory cells of a row through a word line and accessing a memory cell by activating the word line connected to the memory cell, storing an address of an activated word line of the memory bank, refreshing the charge content of all the memory cells of the memory bank, and after the refresh, activating again the word line within the memory bank associated with the stored address.
In accordance with another mode of the invention, a first state of an identifier associated with the memory bank is stored if a word line has been activated in the memory bank and a second state of the identifier is stored if no word line is activated in the memory bank, and after the refresh, the word line associated with the stored address is activated and the identifier is set from the second state to the first state.
In the case of the dynamic semiconductor memory according to the invention, a memory element, expediently a register, is provided on the semiconductor memory itself, in a manner associated with each memory bank to buffer-store that address assigned to the currently activated word line. In principle, it suffices if the address of the activated memory cell is buffer-stored only before a refresh operation. Previously, such information was, at most, buffer-stored in the memory controller. During the refresh, the control device that controls the refresh operation resets all the word lines of a memory bank in order subsequently to automatically activate once again that word line whose address is stored in the register provided therefor. Furthermore, it is expedient to provide a further memory element, expediently as a one-bit register, assigned to a respective memory bank, the activation state of the assigned memory bank being stored in the memory element.
In the event of a refresh command applied externally to the semiconductor memory, in all the memory banks, the word lines are deactivated and pulled to reference-ground potential (command: precharge all). Afterward, the refresh operation is performed for all the memory banks, as explained in the introduction, the procedure being that, in each memory bank, the memory cells of all the rows are in each case read in rows, amplified, and written back again. Following is a reestablishment of the bank state from before the refresh operation for all the memory banks. This means that where the so-called open bit of the second memory element assigned to a memory bank was set, the bank as such is activated and, moreover, that row whose address was stored in the first memory element assigned to the memory bank is activated (command: activate all with reestablishment of the memory state). The functionality for each memory bank thus includes the following: with an activate command directed to the bank, the row address is stored in the first memory element and the open bit is set. The bank is now characterized as activated, as is a row within the bank. The open bit is reset with a precharge command. The address of the previously activated memory cell still remains stored in the first memory element and can be activated again with the next activate command. Compared with the conventional solution incorporating the memory controller, no additional data traffic is generated on the memory bus. The on-chip buffer-storage of the open bit and of the address of the row activated last provides for further automatic and fast reestablishment of the bank state present before the refresh operation.
In accordance with a further feature of the invention, there is provided a second memory element connected to the memory bank and storing data indicating a state of an open word line within the memory bank. The control device is programmed to activate, after refresh, one of the word lines having the address stored in the memory element and to set the state in the second memory element.
In accordance with an added feature of the invention, the control device is programmed, dependent upon a control command applied externally to the semiconductor memory, first to deactivate all of the word lines in the memory bank, then to carry out a refresh for all of the memory cells of the memory bank, and then to activate one of the word lines having the address stored in the memory element.
In accordance with an additional feature of the invention, the memory cells each have a selection transistor with a controlled path and a control terminal and a capacitor connected to the controlled path, and the control terminal is coupled to one of the word lines.
In accordance with yet another feature of the invention, there is provided a word line driver having an output side. The output side is coupled to one of the word lines and the word line driver supplies an activated word line with a high level and a non-activated word line with a low level. Preferably, the low level is a reference-ground potential.
The activation of a word line means that the level thereof is raised until the selection transistors of the memory cells connected thereto are completely turned on. The level usually still lies above the supply voltage that is fed in externally, and is generated by a voltage pump. As a result, the storage capacitors of the memory cells disposed within a row are connected to a respective bit line through the completely turned-on selection transistor. A non-activated word line is connected to reference-ground potential. Reference-ground potential is usually ground. In other applications, the deactivated word line may also be connected to a negative potential to ensure that the selection transistors of the row are completely turned off.
In accordance with yet a further feature of the invention, the at least one memory bank is a plurality of memory banks including a second memory bank, the second memory bank has dynamic memory cells disposed in rows and word lines, the memory cells of a row are connected to and addressed by one of the word lines, the one word line being activated for access of one of the memory cells connected to the one word line, a second memory element is connected to the second memory bank and stores an address associated with an activated one of the word lines, and the control device is programmed to refresh one of the memory banks by resetting all of the word lines of the one memory bank and to activate one of the word lines of the one memory bank having the address stored in the memory element after refreshing the one memory bank.
Depending on the architecture of the semiconductor memory, the memory may have a single memory bank, the memory bank being assigned the register for buffer-storing the address of the currently activated word line. Finally, there are semiconductor memories in which a plurality of memory banks are provided, for example, two or four or even more memory banks. It is then expedient for each of the memory banks to be assigned such a register mentioned above to store there the address of the currently activated word line or the address of the currently open row. In such a case, a memory bank is a unit that is autonomously functional independently of the other memory banks. A memory bank contains an address decoder to select memory cells through activation of word lines and selection of bit lines. The decoders assigned to a memory bank select only word lines and bit lines within the memory bank. Other decoders that operate independently of the first-mentioned decoder are necessary for word lines and bit lines of other memory banks. If a bank is open, i.e., a word line or row of the bank is activated, then, prompted by the opening of the bank and activation of the word line or row, the address of the row assigned to the bank is buffer-stored in the register according to the invention. During a refresh operation, all the rows of the bank are closed and put into the so-called idle state. The invention for the first time makes it possible that, after a refresh operation, the previously open row or word line is opened without the need for an external address transmission.
With the objects of the invention in view, there is also provided a method for operating a semiconductor memory including the steps of providing at least one memory bank having dynamic memory cells disposed in rows, connecting a memory element to the memory bank, addressing the memory cells of a row through a word line and accessing a memory cell by activating the word line connected to the memory cell, storing an address associated with an activated word line in the memory element, refreshing the memory bank with a control device by resetting all word lines of the memory bank, and activating a word line having the address stored in the memory element after the refresh.
In accordance with yet an added mode of the invention, data indicating a state of an open word line is stored within the memory bank in a second memory element connected to the memory bank, and after refresh, one of the word lines having the address stored in the memory element is activated with the control device and the state in the second memory element is set.
In accordance with yet an additional mode of the invention, dependent upon a control command applied externally to the semiconductor memory, the control device first deactivates all of the word lines in the memory bank, then refreshes all of the memory cells of the memory bank, and then activates one of the word lines having the address stored in the memory element.
In accordance with again another mode of the invention, an output side of a word line driver is connected to a word line and a high level is supplied to the word line if the word line activated and a low level is supplied to the word line if the word line is non-activated.
In accordance with a concomitant mode of the invention, there is provided a plurality of memory banks including a second memory bank having word lines and dynamic memory cells disposed in rows. A second memory element is connected to the second memory bank. The memory cells of a row are addressed through a word line and one of the memory cells is accessed by activating the word line connected to the memory cell. An address associated with an activated one of the word lines is stored in the second memory element. One of the memory banks is refreshed by resetting all of the word lines of the one memory bank. One of the word lines of the one memory bank having the address stored in the second memory element is activated after refreshing the one memory bank.
Other features that are considered as characteristic for the invention are set forth in the appended claims.
Although the invention is illustrated and described herein as embodied in a dynamic semiconductor memory with refresh, it is, nevertheless, not intended to be limited to the details shown because various modifications and structural changes may be made therein without departing from the spirit of the invention and within the scope and range of equivalents of the claims.
The construction and method of operation of the invention, however, together with additional objects and advantages thereof, will be best understood from the following description of specific embodiments when read in connection with the accompanying drawings.